Optimal Matrix Multiplication on Fault-Tolerant VLSI Arrays

where h is the decision tree height, or the number of radial cuts, whose i cross edges can be chosen independently: h = (f L-k-l) / (f-1). Therefore, the number of permutations having the number of cross edges i = 1 in a stage-k subgraph of an (3, L) CC-banyan is C;,k=3(3L-k-1)/2, 0 < k < L-2. Now we can evaluate the total number of permutations in CC-banyan with fan-out 3. Theorem 6: The number of permutations in an (f , L) CC-banyan with fan-out f = 3 is ProoJ The expression for the total number of permutations The method of decision trees can also be used for enumeration of all permutations in the case of general fan-out f. We have been able to evaluate the number of permutations in CC-banyans with fan-out f = 4. However, the process of constructing decision trees becomes quite complex and elaborate for large values off. This is due to the fact that the analysis of all possible permutations in a radial sector of size (f-1) becomes a complex combinatorial problem by itself, when f is large. Even so, for practical purposes, the number of permutations for larger fan-outs can be easily obtained by combining analytical expressions (2) and (3) with computer-generated exhaustive enumera-tion for Ci,k. V. CONCLUSIONS In this correspondence, we presented a graph-theoretic approach to the analysis of rectangular CC-banyan networks with an arbitrary fan-out f and an arbitrary number of stages L. It is shown that CC-banyans, like many other networks (e.g., SW-banyans, Benes networks) can be constructed recursively from the networks of smaller size. This recursiveness enables the modular structure of CC-banyans and can be used in the analysis of its partitioning properties. We also presented a general approach to the analysis of permuting properties of CC-banyans. The analytical expressions for the number of permutations performable by CC-banyan with fan-outs 2 and 3 are derived. In the case of general fan-out f , we proposed a method, based on decision tree analysis, for a systematic enumeration of all permutations. Abstract-The Diogenes methodology, proposed by Rosenberg, for the design of easily testable and configurable fault-tolerant VLSI arrays, results in collinear layouts of processors (PE's) that are configured into the desired array structure by appropriate switch settings on buses running parallel to the PE's. While possessing attractive mechanisms for fault-tolerant implementations, Diogenes designs of two-dimensional (2-D) arrays require more area than a …